The present invention relates generally to systems and techniques for trimming a parameter such as input offset voltage of an amplifier to a particular target value by blowing/cutting fuse links, and more particularly to systems and techniques for avoiding the presence of “residual” un-blown or un-cut fuse links after the trimming process is complete. This is because the presence of residual links and corresponding residual trim currents can diminish circuit performance.
The invention also relates to avoiding the need for a-priori knowledge of “trim step” sizes before successful trimming can be initiated. For example, if an operational amplifier is to be trimmed so as to have a particular input offset voltage wherein a differential input transistor pair has a particular transconductance, that results in a particular output current of the differential input transistor pair being applied as input to a folded cascode stage. The junction point or conductor in which that current flows is a good point at which to inject a precise amount of DC current to counter or reduce an initial value of the measured input offset voltage.
Typically, two banks or arrays of fused binarily weighted trim current sources are provided, one on the “positive” side and the other on the “negative” side of the differential input transistor pair. For example, one array of the binarily weighted trim current sources is connected to the collector of a bipolar input transistor (or the drain of an MOS input transistor) on the (+) side of the differential input transistor pair and the other array of the binarily weighted trim current sources is connected to the collector of the bipolar input transistor (or the drain of an MOS input transistor) on the (−) side of the differential input pair. Each binarily weighted trim current source is connected in series with a corresponding un-blown fuse or un-cut laser-cut above link such that all of the binarily weighted “bits”, i.e., current sources initially are “on”. Consequently, a maximum, equal value of trim current initially are injected into the collector (or drain) nodes of each of the (+) and (−) sides of the differential input transistor pair. The differential input transistor pair initially is in a “balanced” condition except for the effects of the initial input offset voltage of the differential input pair, with the maximum possible amount of trim current (or trim voltage or other trim parameter) being initially applied to the collectors (or drains) of the input transistors of both the (+) and (−) sides of the differential input pair. Trimming of the input offset voltage is accomplished by selectively blowing fuses or laser-cutting links, one at a time, in the trim array on one side of the differential input transistor pair, and each time measuring the offset voltage until it has been reduced to an acceptable value.
The above described prior art trimming technique leaves a substantial residual trim current being applied to at least one side of the differential input transistor pair on which no fuses have been blown or on which no links have been laser-cut, because of the presence of residual trim elements still injecting increments of trim current into both the (+) and (−) sides of the differential input pair even after the offset voltage has been trimmed to an acceptable value. The presence of the residual trim elements and corresponding residual trim currents is undesirable because it makes the circuit more susceptible to thermal drift and power supply drift, and may also increase circuit noise and power consumption. This prior art application requires accurate foreknowledge of the trim weights and associated device gain (such as input stage transconductance) and may also require the use of redundant trim bits to account for inaccurate a-priori information.
In another typical prior art application, a single bank or array of weighted trim elements can be turned on and applied either in the positive direction or the negative direction, i.e., applied to either the positive side or the negative side of the differential input transistor pair. The magnitude of the trim elements is determined by an initial measurement and a calculation based on the a-priori weights of the trim cells. This prior art application also requires accurate foreknowledge of the trim weights and associated device gain (such as input stage transconductance) and may also require the use of redundant trim bits to account for inaccurate a-priori information.
Thus, there is an unmet need for an improved differential trimming technique that reduces input offset voltages associated with a differential input stage and also reduces thermal drift, power supply drift, circuit noise, and/or power consumption of the differential input stage.
There also is an unmet need for an improved differential trimming technique that reduces input offset voltages associated with a differential input stage and also reduces or eliminates the presence of residual trim elements and corresponding residual trim currents associated with prior art differential integrated circuit trimming techniques even after the prior trim processes have been completed.
There also is an unmet need for an improved differential trim technique which does not depend on accurate a-priori knowledge of trim bit weights or device characteristics.